Design space exploration for layer-specific efficiency enhancement in CNN accelerators

Deploying specific convolutional neural networks (CNNs) on target FPGA boards presents a significant challenge: fully utilizing on-chip resources while maintaining efficient accelerator operation under bandwidth and resource constraints. This paper presents an automated hardware/software co-design methodology for FPGA-based CNN accelerators. A flexible and configurable accelerator architecture is developed in conjunction with a Design Space Exploration (DSE) engine to identify optimal configurations for a given network under the resource constraints of a target FPGA device. The DSE algorithm explicitly accounts for the heterogeneous computational characteristics and bandwidth demands of different convolutional layers. By configuring layer-specific data cache sizes through software instructions, DSP computational efficiency is enhanced, enabling the accelerator to consistently approach peak computational capability. Experimental results across multiple neural networks and FPGA platforms show that the execution time predicted by the proposed DSE-based automated design methodology deviates by only 3.8% from measured deployment results. Furthermore, the proposed approach achieves up to a 1.83×improvement in resource utilization efficiency and overall performance compared with prior methods.