Demonstration of Performance Enhancement in Semiconductor Devices Utilizing TiO₂-Based High-k Triple-Layer Dielectric

In order to compensate for the trade-off relationship between the dielectric’s bandgap and its dielectric constant, a triple-layer dielectric structure composed of high-k dielectrics including TiO₂ was simulated. It was verified that an optimal balance between leakage current and device performance could be found by using a MOS capacitor structure with the multiple dielectric layers. Additionally, drain current analysis using a MOSFET structure confirmed that this approach can enhance electrical properties compared to using a single layer dielectric. This study suggests a process method that offers more options for satisfying device performance requirements and indicates its potential for application in various fields.