Subtractive-Dither-Assisted Background Calibration for Linearity Enhancement in Pipelined ADCs for IIoT Applications

This paper presents a subtractive-dither-assisted background calibration technique for a 2 GS/s 12 bit pipelined analog-to-digital converter (ADC). A large 7 bit pseudo-random dither is injected in both the flash and the multiplying digital-to-analog converter (MDAC) to decorrelate the differential nonlinearity (DNL) errors caused by the inherent quantization error nonlinearity, capacitor mismatching, and inter-stage amplifier nonlinearity from the input signal. Designed in a 28 nm CMOS process with a 1 V supply, post-layout simulations demonstrate a 10.2 dB improvement in spurious-free dynamic range (SFDR), from 73.8 dB to 84.4 dB, with dithering enabled under a close-to-Nyquist input frequency of 985 MHz. Although the injected dither cannot be completely removed in the digital domain, the proposed ADC exhibits only a 0.5 dB degradation in signal-to-noise-and-distortion ratio (SNDR) for full-scale input, achieving an SNDR of 62.3 dB and an effective number of bits (ENOB) of 10.1 bits. Dithering also improves static performance, with DNL and INL optimized to +0.54/−0.53 LSBs and +0.85/−0.88 LSBs, respectively. Moreover, the proposed dither-based calibration technique introduces an additional power consumption of less than 2 mW.