Research reveals enhanced patterning at sub-8 nm scale using interfacial engineering in lithography, suggesting improved chip technology.
In the Research Article (e24320), Ni Zhen, Lei Zhang, and co-workers report the atomic-level interfacial engineering of tin oxo cluster photoresists by decorating silane moieties. The exposed Sn-O-Si and Si-O-Si networks have significantly enhanced both multiple crosslinking and substrate adhesion, giving rise to high-fidelity patterning at the sub-8 nm scale. This work provides a potential material design strategy for next-generation ultrahigh resolution lithography in advanced chip technology nodes.
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Wei et al. (2026) studied this question.
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