Electrical characterization of interface and near interface trap distributions for 3C-SiC/Al2O3 vertical MOS capacitors

Abstract This work systematically characterized the density distributions of interface traps ( D it ) and near interface traps (NITs) for 3C-SiC/Al 2 O 3 metal-oxide semiconductor (MOS) capacitors without and with annealing treatments (300 °C and 400 °C for 60 s). Capacitance–voltage measurements demonstrated that annealing effectively reduced flat-band voltage shift, hysteresis, and effective fixed charge density. Samples annealed at 400 °C exhibited the lowest D i t , ranging from 1.6 × 10 11 cm −2 eV −1 to 3.2 × 10 10 cm −2 eV −1 , within the range of 0.2–0.6 eV from the conduction band edge of 3C-SiC. Furthermore, the NIT density was quantitatively characterized by a distributed circuit model based on the frequency-dependent capacitance under the accumulation condition, and two possible NIT distribution (exponentially-decaying and uniform) assumptions were considered. The exponentially-decaying distribution possessed better fitting for each sample. It was found that NIT density at the interface ( N NIT0 ) decreased and the attenuation coefficient ( α ) increased after annealing, indicating NITs were effectively passivated. The areal NIT density was extracted by integral, which significantly decreased from 5.3 × 10 13 cm −2 eV −1 to 2.4 × 10 13 cm −2 eV −1 by annealing. This study confirms that combining Al 2 O 3 with an appropriate annealing is an effective method for improving 3C-SiC MOS interface quality.