This research develops a predictive model to assess leakage behavior in NMOS transistors, suggesting implications for digital circuits.
The goal of this research is to develop a predictive model that determines how low-frequency Electromagnetic Interference (EMI) affects the leakage current behavior of CMOS transistors. Although developed and validated using NMOS devices, the modeling framework can be extended to PMOS transistors; experimental validation of PMOS devices is planned for future work. The model provides essential physical parameter-based analysis of nanoscale device EMI susceptibility during low-frequency operation. The model demonstrates high accuracy and practicality through experimental verification of test chips built with standard TSMC CMOS technology nodes. The findings highlight that modern CMOS designs must account for low-frequency EMI, which can induce leakage shifts significant enough to impact EMC compliance, functional robustness, and reliability in ultra-low-power and near-threshold applications. The research delivers a practical method for designers to evaluate and reduce EMI-induced leakage in integrated circuits.
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Abedi et al. (2026) studied this question.
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