High‐Mobility and Low‐Voltage Top‐Gate Transistors Comprising an InSnO–InSnWO Channel Layer and a Polymethyl Methacrylate Dielectric Layer

The thin‐film transistor (TFT) composed of an InSnWO thin film deposited via magnetron sputtering as the channel layer and a polymethyl methacrylate thin film prepared using the solution method as the dielectric layer is fabricated. The influences of the W target sputtering power during the preparation of the channel layer and the channel layer structure on the device performance are systematically investigated. Increasing the W target sputtering power increases W content, thereby suppressing the formation of oxygen vacancies and decreasing the electron carrier concentration in the channel layer, resulting in reduced off‐state current and a positive shift in the threshold voltage of the single‐channel layer TFT. In addition, a dual‐channel layer structure composed of InSnO and InSnWO layers with high and low electron carrier concentrations, respectively, is prepared by introducing an InSnWO layer between the dielectric layer and the InSnO layer. The resistance of the dual‐channel layer and the gate‐voltage‐modulated carrier density are adjusted by optimizing the thickness ratio, thereby enabling the independent control of key parameters regarding device performance. The resulting dual‐channel layer TFT exhibits excellent performance with a high mobility (67.11 ± 0.82 cm 2 V −1 s −1 ) and a low threshold voltage (0.40 ± 0.01 V).