0DSTL ESP32-P4 KiCad Footprints (25x25 1.0mm Pitch / 27x27 1.25mm Pitch) + 3D Models

This repository contains KiCad footprints and 3D models for the ESP32-P4 module. Included:- 25x25 mm variant (88 pins, 1.0 mm pitch)- 27x27 mm variant (80 pins, 1.25 mm pitch)- Matching STEP 3D models- Pinout definitions The 3D models were created based on publicly available datasheet dimensions.No proprietary CAD data was used. This is not an official model provided by Espressif. ESP32 is a trademark of Espressif Systems.This project is not affiliated with or endorsed by Espressif Systems. MIT License Copyright (c) 2026 0DSTL Permission is hereby granted, free of charge, to any person obtaining a copyof this software and associated documentation files (the "Software"), to dealin the Software without restriction, including without limitation the rightsto use, copy, modify, merge, publish, distribute, sublicense, and/or sellcopies of the Software, and to permit persons to whom the Software isfurnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in allcopies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ORIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THEAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHERLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THESOFTWARE. 🔗 Community: https://zenodo.org/communities/0dstl-architecture Summary Most recent relevant documents from 0DSTL: V1. LTspice Simulations (QC vs. GenX).pdf EQPU_0DSTL_Simulation_Results_arXiv.pdf 0DSTL_Vs_Default_Ceff.pdf V5. Whitepaper_EQPU_0DSTL V5.pdf V6. 0DSTL Security & Extras.pdf V7. The first complete analog transformer core (Digital intepreted) xxxxxx Bit In, xxxxxx Bits Out Full_Analog_Digital_Operation_Formalization.pdf LTspice Simulation V4.rar V8. Analog Sigma Delta Core Appendix_A_0DSTL.pdf LTspice Simulation V4.rar V10. 0DSTL: ESP32 Analog Coprocessor