Towards a Femtosecond-Coherent Compute Architecture: Optical Baseclock Distribution with Local Pulse Amplification for the Elimination of Clock-Domain Synchronisation Overhead

We propose a three-layer architecture in which local pulse amplifiers at compute-cluster boundaries enable an optically broadcast femtosecond baseclock across heterogeneous compute systems, structurally eliminating inter-domain synchronisation infrastructure. The core contribution is the systematic evaluation of three candidate amplifier technologies against a four-stage jitter budget derived from published device parameters, combined with a quantified overhead analysis establishing the scale of the problem. The architecture targets a specific structural cost: the PLLs, synchroniser chains, and FIFO buffers required at clock-domain boundaries in modern heterogeneous SoCs, estimated at 10–15% of total chip power (sensitivity range: 5–20%). At global scale, this overhead represents on the order of 0.5–1 GW of AI-datacenter power. Electrical clock distribution cannot maintain phase coherence across a large die at multi-GHz rates; optical clock distribution can deliver femtosecond-precision timing, but fanout loss in photonic splitter networks limits the number of synchronised endpoints. The unsolved problem is local pulse amplification: a device that can receive an attenuated femtosecond optical pulse and regenerate it at operating energy within a coherent timescale. We evaluate three candidate technologies — quantum dot semiconductor optical amplifiers (QD-SOAs), injection-locked micro-lasers, and erbium-doped waveguide amplifiers (EDWAs). Injection-locked micro-lasers emerge as the strongest candidate, with 20 fs RMS timing jitter already demonstrated and a unique jitter-cleaning property. QD-SOAs offer the simplest waveguide-compatible integration path on CMOS-compatible silicon. EDWAs approach the quantum-mechanical noise-figure limit of 3 dB but carry higher per-node pump power costs. All three candidates operate at room temperature and have demonstrated integration paths to silicon photonic platforms. The jitter budget analysis uses published device parameters; the specific configuration — these amplifiers operating as clock-pulse amplifiers at GHz repetition rates — has not been directly characterised, and the estimated jitter ranges should be read as order-of-magnitude bounds pending experimental confirmation.