Silicon lateral avalanche photodiodes fabricated by standard 0.18 µm CMOS process

宏一 飯山; 武男 丸山; Koichi Iiyama; Hideki Takamatsu; Takeo Maruyama

doi:10.24517/00007868

January 1, 2009Open Access

Silicon lateral avalanche photodiodes fabricated by standard 0.18 µm CMOS process

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Key Points

This research aims to fabricate silicon lateral avalanche photodiodes (APDs) using a standard CMOS process and evaluate their performance.
Utilized a standard 0.18 µm CMOS fabrication process.
Measured the avalanche gain and bandwidth at varying bias levels.
Achieved a maximum avalanche gain of 224 at 8 V bias.
Bandwidth measurements showed 1.6 GHz for low avalanche gain and 800 MHz for high gain.

Implication

Fabrication of silicon avalanche photodiodes shows high gain and bandwidth, indicating efficient photodetection capabilities.

Abstract

A Si APD was fabricated by standard 0.18 μm CMOS process. The maximum avalanche gain was 224 for only 8 V bias. The bandwidth was 1.6 GHz for low avalanche gain and 800 MHz for large avalanche gain.

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Cite This Study

飯山 et al. (2009) studied this question.

synapsesocial.com/papers/69cd7b275652765b073a8f69 https://doi.org/10.24517/00007868

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Silicon lateral avalanche photodiodes fabricated by standard 0.18 µm CMOS process

Key Points

Implication

Abstract

Discussion

Cite This Study

Silicon lateral avalanche photodiodes fabricated by standard 0.18 µm CMOS process

Key Points

Implication

Abstract

Discussion

Cite This Study

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