Design of Triple Node Upset Self-recoverable Latch Based on Dual-output ACE-elements

As CMOS technology developing pushes towards the scaling in feature size of transistors, radiation-induced multi-node upsets in CMOS circuits now pose a key reliability challenge to storage devices. To address the issue of low robustness of storage devices, this paper proposes a Low-Cost Triple-Node-Upsets-Recovery Latch (LCDOAL). The LCDOAL latch consists of four DOACEs and four CG-DOACEs. By implementing interlocking connections between DOACEs and CG-DOACEs, the LCDOAL latch forms a feedback loop and effectively achieves self-recovery from TNUs through data feedback. The proposed latch uses clock-gating technique to reduce power consumption. HSPICE simulation results indicate that LCDOAL achieves average savings of 1.96% in area, 7.1% in transmission delay, 66.1% in power consumption, and 70.6% in Area-Power-Delay Product (APDP), compared to the five typical TNU self-recovery latches (IHTRL, LCTNURL, TRLW, TNU-SR, and TSRL). Furthermore, the LCDOAL latch exhibits low sensitivity to Process, Voltage, and Temperature (PVT) variations.