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We show that downscaling the top-contact length to 13nm induces no penalty on the electrical characteristics for CVD MoS 2 FETs. We demonstrate this for devices with different gate-oxides and operating in both channel and contact-limited regimes, thus confirming carrier injection at the edge of the contact metal. Consequently, we have scaled the device footprint achieving an I on =250μA/μm and excellent SS min =80mV/dec for 50nm SiO 2 and 4nm HfO 2 gate oxides, respectively.
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Smets et al. (2019) studied this question.
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