A Low Power 16-bit 125MS/s Pipeline ADC with 100dB SFDR

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This paper presents a low-power 16-bit 125 MS/s pipeline analog-to-digital converter (ADC). A switched-capacitor dynamic bias technique is proposed to reduce power consumption while maintaining excellent performance. An enhanced bootstrapped switch is implemented to improve the linearity further. The pipeline ADC is fabricated in a 0.18μm mixed signal complementary metal–oxide–semiconductor (CMOS) process with an area of 1.8mm2. The implemented ADC is measured at 125 MS/s conversion rate under 1.8 V supply, and it achieves beyond 100 dB spur-free dynamic range (SFDR) and 75.9 dB signal-to-noise ratio (SNR) after foreground calibration for capacitor mismatch errors while the power consumption is 189mW resulting in 0.3 pJ/conv.-step FoM (Figure-of-Merit).