A 1.2-V 250-mW 14-b 100-MS/s Digitally Calibrated Pipeline ADC in 90-nm CMOS

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This paper describes a digitally calibrated pipeline analog-to-digital converter (ADC) implemented in 90 nm CMOS technology with a 1.2 V supply voltage. A digital background calibration algorithm reduces the linearity requirements in the first stage of the pipeline chain. Range scaling in the first pipeline stage enables a maximal 1.6<formula formulatype="inline"><tex Notation="TeX">\ Vₚₚ</tex></formula> input signal swing, and a charge-reset switch eliminates ISI-induced distortion. The 14b ADC achieves 73<formula formulatype="inline"> <tex Notation="TeX">$~$</tex></formula>dB SNR and 90 dB SFDR at 100 MS/s sampling rate and 250<formula formulatype="inline"><tex Notation="TeX">$~$</tex></formula>mW power consumption. The 73 dB SNDR performance is maintained within 3 dB up to a Nyquist input frequency and the FOM is 0.68<formula formulatype="inline"> <tex Notation="TeX">$~$</tex></formula>pJ per conversion-step. </para>