Junctionless Field Effect Diode (JL-FED): A First-Principles Study

This paper proposes a novel field effect diode (FED) for the first time namely junctionless FED (JL-FED). Our simulation results show that JL-FED gives the combined advantages of conventional FED and JL field effect transistor (JL-FET). In fact, not only fabrication process of the JL-FED is easier than FED, but also unlike a FED, JL-FED device turns on without applied biases to the control gates. Furthermore, to reduce the leakage current of the JL-FED structure, we propose modified JL-FED (MJL-FED) structure, in which the control gates work functions are different from that of JL-FED. The digital performance parameters such as ION/IOFF ratio and subthreshold slope (SS) for MJL-FED are investigated using 2-D simulations. MJL-FED offers superior ION/IOFF ratio and SS than its JL-FED counterpart having same dimensions. Our simulation results show that MJL-FED provides channel length scaling possible down to 10 nm, and it is a reasonable candidate for logic transistor applications.