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Advanced Turing-patterned Ta2S3 reduces Cu diffusion barrier in semiconductor technology, suggesting improved interconnect performance.
As semiconductor technology advances towards the 15-Å node and beyond, the back-end-of-line (BEOL) metal interconnect technology encounters severe scaling challenge, because the conventional barrier/liner TaN/Ta(Co) bilayer cannot be proportionally thinned down as the pitch size shrinks. This challenge arouses significant resistance-capacitance (RC) delay that is currently the bottleneck for advanced integrated circuits. Herein, we propose a Turing-patterned Ta₂S₃ (Tp-Ta₂S₃) thin barrier to address the above interconnect scaling challenge. The Tp-Ta₂S₃, synthesized by a particularly designed energy-enhanced atomic layer deposition (ALD) process, features a labyrinthine stripe morphology with an intertwined layer structure, which can significantly enhance its Cu diffusion barrier performance by forcing the Cu atoms to migrate a significantly longer path through the 2D interlayer space. The synthesized Tp-Ta₂S₃ barrier with only 1.2 nm thickness exhibits excellent Cu wettability, remarkably strong adhesion, and much better barrier performance than the state-of-the-art TaN barrier.
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Tian et al. (2026) studied this question.
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