A 24-30-GHz 4-Element Phased-Array Receiver Using Phase-Shifting-First Architecture with 9.9-mW/Element Power Consumption

This paper presents a 24–30-GHz 4-element phased-array receiver for millimeter-wave 5G communication applications. Low noise amplifier and phase shifter in the receiver are merged into one block to construct a phase shifting first architecture. A low noise phase shifter (LNPS) topology is proposed to improve gain and reduce noise figure of a vector-sum phase shifter (VS-PS). The LNPS is based on a current-sharing CG-CS-CG three-stage amplifier. Quadrature hybrid couplers are inserted into the CG-CS-CG amplifier to construct a vector-sum phase shifter. The DC and RF path of the proposed phase shifter are elaborately designed to ensure the balance of orthogonal modulation. The entire LNPS shares a single DC supply to save power. Apart from the LNPS located at the first stage, each receiver element integrates a programmable gain amplifier (PGA) to provide amplitude adjustment, and a low power control block to offer the RF blocks precise control. The designed receiver, fabricated in 40-nm CMOS technology, achieves a very low power consumption of 9.9-mW/element and occupies a small chip area of 0.304-mm2/element. Single channel measurement result (including power combiner) shows that the peak gain and noise figure of the proposed receiver are 12.8 dB and 4.6 dB on reference state, respectively. The receiver exhibits 6-bit phase resolution with root-mean-square (RMS) phase error of less than 1.94° over 24–30-GHz. The receiver also results in a 4-bit gain control performance with RMS gain error of less than 0.5-dB (15-dB gain tuning range with step of 1-dB).