FPGA-Based Design and Implementation of a High-Performance Telemetry Transmission Architecture for Satellite Communications

This paper presents a high-performance and resource-efficient Field Programmable Gate Array (FPGA)-based architecture for satellite telemetry transmission systems. The proposed design implements a flexible channel coding chain, including Reed–Solomon (R-S) encoding, convolutional encoding, symbol interleaving, pseudo-randomization, and Attached Synchronization Marker (ASM) insertion, in accordance with CCSDS recommendations. The architecture is fully integrated and configurable, allowing dynamic selection of coding schemes without requiring structural modifications. The system is implemented on a modern FPGA platform with a 32-bit AXI4-Stream interface at 110 MHz, reaching an effective throughput of up to 1.76 Gbps. Experimental results demonstrate reliable timing with positive setup and hold margins, allowing the system to operate at approximately 130 MHz. Power consumption is measured using Switching Activity Interchange Format (SAIF)-based switching activity, providing a realistic estimate of programmable logic power consumption. The total on-chip power is about 1.77 W for individual coding modes. It rises to 1.91 W in the concatenated setup, which is the worst-case scenario. The results show that the proposed architecture efficiently uses resources, runs reliably at high speeds, and exhibits predictable power consumption. This makes it well suited for high-reliability and energy-constrained satellite communication systems. resources are used.