Understanding the Interplay between CdSe Thickness and Cu Doping Temperature in CdSe/CdTe Devices

CdSe thickness and Cu doping play significant roles in achieving a highly efficiency in CdTe solar cells. Using an evaporated CdSe/CdTe device stack to avoid vacuum breaks between layers, we investigate the role of the CdSe thickness on the device performance and show that when the CdSe thickness is above a critical value the device performance, specifically the short circuit current (J <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SC</inf> ), suffers. From these measurements, we determine the critical thickness of CdSe to be 120 nm. However, in some cases the CdSe thicknesses can be increased above the critical value and increasing the Cu doping process temperature can lead to an increase in J <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SC</inf> and an overall improvement in device efficiency. Specifically, for a device with ~270 nm of CdSe, the J <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SC</inf> increases from 7.9 mAcm -2 with CuCl <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> processing temperature of 200 °C to ~29 mAcm -2 when the processing temperature is increased to 250 °C.