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The cause of failures in insulated gate bipolar transistor (IGBT) modules is primarily attributed to temperature-related factors. Accurately estimating the junction temperature of IGBT modules is crucial for enhancing their reliability. Currently, thermal network models stand as commonly used tools for estimating the junction temperature of IGBT modules. However, prevailing thermal models exhibit certain limitations in accurately predicting the junction temperature, particularly when considering the degradation of chip solder within IGBT modules. This article presents a practical degradation model of the chip solder layer, establishing a functional correlation between the chip solder degradation rate and the number of power cycles. A dynamic compact thermal network model over long time scales is established, and the method for thermal parameter extraction is discussed. The finite-element simulation and experimental results show that the dynamic compact thermal network model can accurately estimate the junction temperature.
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Ma et al. (2024) studied this question.
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