Challenges and Mitigations of Microbumps Pitch Scaling for Chiplet Applications

This paper explores the challenges of microbump pitch scaling down to 5 μm for chiplet applications, including TCB tool alignment accuracy, fabrication process limitations, CTE mismatch, metal oxide reduction, and reliability concerns for die to wafer bonding. An approach called embedded bumps together with fluxless TCB are introduced to mitigate the challenges. Additionally, it discusses qubit, interposer and CMOS chips integration in 2.5D chiplet and 3D architectures for cold and quantum computing applications, where indium is used as the solder metal where successful bonding results for 20 μm pitch indium bumps are shown.