UASR‐A: An Efficient Edge Super‐Resolution Accelerator With Hardware‐Algorithm Co‐Design Techniques

Deploying high‐performance super‐resolution (SR) on resource‐constrained edge devices remains challenging due to computational complexity, inefficient operators and memory bandwidth limitations. We propose a hardware‐algorithm co‐design solution comprising the lightweight unified‐attention super‐resolution network (UASR) algorithm and the high‐efficiency UASR‐A accelerator. Algorithmically, we introduce a convolution‐transformer (ConvFormer) hybrid architecture featuring the unified‐attention mixer (UA‐M) and the reparameterized edge‐extraction feed‐forward network (REFN) to optimize the quality‐efficiency trade‐off. Architecturally, UASR‐A employs compact non‐linear operators, PixelShuffle and a row‐buffer pipeline with block‐based computing to minimize off‐chip memory access. Implementation on the Xilinx ZCU102 platform shows that UASR‐A achieves the best reconstruction quality among the compared FPGA‐based SR accelerators. In particular, compared with LSR [1], it improves PSNR by 0.15 dB on Set5 and 0.37 dB on Set14. It also reduces DSP usage by 74.3%.