This paper presents an advanced FPGA-based framework for the analysis and performance evaluation of Finite Impulse Response (FIR) filters for image denoising applications, leveraging their inherent stability, linear phase characteristics, and implementation efficiency in digital signal processing. The proposed approach focuses on optimizing the FIR filter architecture specifically for FPGA platforms to achieve high- speed, low-latency processing of image data through parallelism and efficient resource utilization. A Gaussian noise-corrupted image is used as the input to systematically evaluate the denoising capability of various FIR filter configurations, with particular emphasis on achieving an optimal balance between noise suppression and preservation of critical image details such as edges and textures. The experimental results demonstrate that the FPGA-based implementation significantly outperforms conventional software-based methods in terms of processing speed, real-time capability, and noise reduction effectiveness, thereby highlighting its suitability for performance-critical applications such as medical imaging, satellite image analysis, and video surveillance systems, while the complete design is synthesized and validated using Xilinx Vivado 2018.3, confirming its practical feasibility for deployment in high- performance embedded.
Krishna et al. (Thu,) studied this question.