The Design of FIR Filter Based on improved DA Algorithm and its FPGA implementation: REVIEW

This research investigates challenges in employing the Distributed Arithmetic (DA) algorithm for Finite Impulse Response (FIR) filters on Field-Programmable Gate Arrays (FPGAs). Focusing on coefficient representation, it explores precision trade-offs via fixed-point arithmetic and quantization. Memory optimization strategies, such as efficient storage within FPGA resources, are analysed to reduce memory requirements. Enhancing computational speed involves optimizing lookup table access and architectural modifications. Efficient management of FPGA resources and trade-offs between latency, throughput, and resource usage are also explored. Algorithmic refinements specific to DA-based FIR filters are studied to enhance resource utilization and computational efficiency. Overall, this work offers insights and solutions spanning algorithm design, memory utilization, lookup table speed, and FPGA architecture for more efficient DA-based FIR filter implementations on FPGAs.