Key result
The Finite Impulse Response Adaptive Filter using distributed arithmetic circuits reduced delay and hardware requirements compared with conventional methods.
Why the study?
Emerging technologies in DSP systems require high performance, and adaptive filtering designs need modification to reduce delay and hardware requirements.
The proposed FIR adaptive filter using distributed arithmetic circuits reduces hardware requirements and delay compared to conventional designs.
May enable efficient cardiac signal hardware; leaves open clinical validation before device adoption.
Emerging technologies in DSP systems require high performance in order to provide optimal performance. In addition, Adaptive Filtering plays a key role in the implementation of a variety of digital signal processing algorithms and it can change their characteristics to achieve desired output. VLSI implementations of these designs are efficiently used for filtering and communication. This project proposes design of Finite Impulse Response (FIR) Adaptive Filter which employs distributed arithmetic (DA) circuits for availing improvement in performance. DA circuits explicitly reduces the number of partial product generation. That is existing Design is modified to reduce the delay and hardware requirements. In modified filter, the number of adders and multipliers are reduced which effectively enhances the speed of computation. The VLSI design for 8, 16, 32 and 64 taps are analyzed and compared. These designs are implemented using Altera Quartus II software with family stratix II and device EP2C70F896C6 and the results are reported. The results shows that the Filter design using distributed arithmetic circuits offers good performance when compared with Conventional method.
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G. Sahaana (2022) studied Biomedical Signal Processing. Finite Impulse Response (FIR) Adaptive Filter using distributed arithmetic (DA) circuits vs. Conventional method was evaluated on Delay and hardware requirements. The Finite Impulse Response Adaptive Filter using distributed arithmetic circuits reduced delay and hardware requirements compared with conventional methods.
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