An Area and Power-Efficient Adaptive FIR Filter Architecture for Decision Feedback Equalizers

In this project, a memory less distributed arithmetic based adaptive FIR filter has been proposed for low power and area efficient design. The area and power of the design is decreased, because of using memory less distributed arithmetic architecture in the adaptive FIR filter for computing the inner product. The LUT in the conventional Distributed Arithmetic (DA) based filter is replaced by 2:1 multiplexers in the proposed design to reduce the area. By using enhanced 4:2 compressor adder instead of normal adder, the area of the filter further reduced. The proposed design requires more than half area that required for the existing LUT based inner product block. The proposed design is implemented in synopsis 90nm CMOS technology. The synthesis result shows that the area of the proposed design is reduced by 52.79% when compare with existing architecture. Also, the proposed Adaptive filter causes 69.25% less power consumption for filter tap N=16, 32 and 64. Proposed design provides 36.50% less Area Delay Product (ADP) and 30% less in Power Delay Product (PDP) when compare with the pipelined DA based adaptive FIR filter.