Energy-Optimized Multiplier-Less FIR Filter for Reconfigurable Biomedical Systems

This is the authors' abstract. We don't add key points for this paper.

Low-power reconfigurable finite impulse response (RFIR) filters are important in portable biomedical signal-processing systems, where area, power consumption, and timing overhead must be minimized. This paper presents a multiplier-less RFIR filter architecture based on shared input decoding and coefficient multiplication block (CMB)- based shift-add realization. In the proposed architecture, the input sample is decoded into selection, shift, sign, and nonzero control signals, and coefficient multiplication is performed using multiplexer-assisted shift-add operations instead of conventional multipliers. This reduces redundant decoding hardware, arithmetic complexity, and switching activity in the product-generation stage. The architecture is implemented in Verilog HDL and synthesized using Synopsys Design Compiler with the SAED 32 nm standard-cell library. For 32-tap and 64-tap RFIR implementations, the proposed design achieves up to 85.19% reduction in area-delay product (ADP) and up to 82.64% reduction in powerdelay product (PDP) compared with selected existing programmable FIR filter architectures. Standard FIR benchmark filters are also evaluated to verify the behavior of the proposed architecture across different coefficient sets and tap lengths, where ADP and PDP reductions of up to 62.40% and 59.51%, respectively, are obtained. The reduced PDP values indicate improved energy-oriented performance under the same synthesis conditions. An ECG denoising case study is included to demonstrate the applicability of the proposed RFIR architecture for biomedical signal-processing applications.