An Efficient VLSI Architectures for FIR Filter in Fixed and Reconfigurable Applications

Recently, with the development of Software Defined Radio (SDR) technology FIR filters have been concentrated on reconfigurable implementation.The filter coefficients in reconfigurable filters change dynamically in run time.In biomedical applications like Electro Cardio Gram (ECG) the coefficients of FIR filters remain fixed.So there is need to implement a Reconfigurable and Fixed FIR filter structure to support multi-standard communications.The need for reducing the area while increasing the computational speed is still felt.This paper addresses the problem of developing a high-speed and area efficient VLSI architectures for FIR filter in Fixed and Reconfigurable applications.The proposed architecture is compared with that of RFIR and FFIR filters using Ripple Carry Adder (RCA) and Carry Select Adder (CSLA) in Pipelined Adder Unit in terms of Area Delay Product(ADP).The proposed architecture has a better ADP than a RFIR and FFIR filter with RCA by 14.8% and 4.51% and is better than RFIR and FFIR filter with CSLA by 19.4% and 17.9%.