Design of Majority Logic Decoder for Error Detection and Correction in Memories

Due to augmenting integration densities, technology scaling and variation in parameters, the performance failures would possibly occur for every application. The memory applications are vulnerable to single event upsets and transient errors which may cause malfunctions. This paper deals with the idea of a totally distinctive fault detection and correction technique using EG-LDPC codes with the applying mainly targeted on reminiscences. The majority logic secret writing is used here, since it will correct associate degree outsize type of errors. Albeit the majority secret writing consumes longer, it will be overcome by the projected technique that detects the errors in less cycle time. It will clearly reduce operation time once the information scan technique is error free. the employment of associate degree additional logic finishes up during a little house overhead in projected methodology once place next to the current technique, that's overcome by a revised implementation of majority gate.