Design and development of transmission gate-PFAL-based FIR filter utilizing efficient hybrid adders for low-power VLSI systems

This paper presents the design and development of a low-power Finite Impulse Response (FIR) filter based on Transmission Gate–Positive Feedback Adiabatic Logic (TG-PFAL) for energy-efficient VLSI systems. The proposed TG-PFAL logic is utilised to implement Efficient Hybrid Half Adders (EHHA) and five Efficient Hybrid Full Adders (EHFA-1 to EHFA-5) with optimised power and delay characteristics. These adders are further employed to construct 16-bit Carry-Save Adders (CSAs) and high-speed 8-bit multipliers, including Wallace and Dadda multipliers. The developed arithmetic modules are integrated into 4-tap and 8-tap FIR filter architectures with an 8-bit input word length. All circuits are designed and simulated in Cadence Virtuoso using GPDK 90 nm CMOS technology and evaluated under CMOS, PFAL, and TG-PFAL logic styles. Simulation results show that Dadda multiplier-based FIR filters outperform Wallace multiplier-based implementations across all logic families. The proposed TG-PFAL-based EHFA-5 FIR filter achieves power reductions of 73.32% to 78.12% compared to CMOS and 35.78% to 41.90% compared to PFAL, along with delay improvements of 25.39% to 27.15% over PFAL implementations. The combined reduction in power and delay leads to a significant improvement in power-delay product (PDP), demonstrating the effectiveness of TG-PFAL for scalable, high-speed, and low-power arithmetic and DSP architectures.