A 54.5 GHz to 71.0 GHz Phase Inverting Variable Gain Amplifier With 18.0 dB Gain Tuning Range in a 65 nm CMOS Process

This paper presents a Phase Inverting Variable Gain Amplifier (PIVGA) in a 65 nm CMOS Process. The circuit consists of a three‐stage differential amplifier followed by a passive attenuator. The first stage employs a cross‐coupled differential amplifier to perform phase inversion of the input signal. The second and third stages utilize a dual‐gate differential amplifier to achieve high gain, while two consecutive passive attenuators are implemented to enable fine gain control with 1.5 dB steps, resulting in a total gain tuning range of 18.6 dB. The PIVGA achieves a maximum gain of 13.5 dB at 63.0 GHz, with a 3‐dB bandwidth ranging from 54.5 GHz to 71.0 GHz, covering a wide portion of the V‐band. The maximum RMS phase error and gain error across the operational frequency range are 3.5° and 0.38 dB, respectively. The measured input 1‐dB compression point (IP1dB) is −10.5 dBm at 60 GHz frequency. Finally, the power consumption is 30.2 mW with 1.0 V supply voltage, and the chip occupies an area of 0.55 mm².