A 31–36 GHz low noise‐variable gain amplifier with less than 0.37° RMS phase error and 0.4 dB gain step in 65‐nm CMOS

This article realizes a low noise‐variable gain amplifier (LN‐VGA) operating at the frequency range of 31–36 GHz. The LN‐VGA consists of two amplifier stages and a gain control stage. To achieve low noise and high gain, the two amplifier stages were implemented using a single‐ended inductive source‐degeneration cascaded with pseudo‐differential neutralization capacitors. Moreover, a symmetrical splitting cascode unit topology is proposed in the gain control stage to improve the precision of phase variation and gain step within the 3‐dB bandwidth. The LN‐VGA was fabricated using a 65‐nm CMOS process, demonstrating a gain control range of 15.2–21.2 dB with less than 2° phase variation and a minimum noise figure of 5.6 dB. The measured results show less than 0.37° rms phase error and a 0.4 dB gain step at 31–36 GHz. The chip occupies an area of 0.81 × 0.51 mm 2 excluding pads and consumes 27 mW of power.