A Fractional Output Divider With Background DTC Calibration Using a Time‐Amplifier‐Based BBPD

This work presents a high‐performance open‐loop fractional output divider (FOD) incorporating a dual‐path digital‐to‐time converter (DTC) architecture with background calibration for DTC gain error. The calibration scheme employs a time‐amplifier (TA)‐based bang‐bang phase detector (BBPD) to reduce the dead‐zone of phase detection, enabling precise convergence of the calibration loop. In addition, a hybrid calibration scheme combining the successive‐approximation (SAR) algorithm and least‐mean‐square (LMS) algorithm is introduced to accelerate calibration without compromising accuracy. Fabricated in a 40 nm CMOS process, the proposed FOD occupies a core area of 0.022 mm 2 and supports an output frequency range of 10–250 MHz. At an output frequency of 123.775 MHz, it achieves a 10 kHz–20 MHz integrated rms jitter of 1.889 ps rms and a spur level of −50.330 dBc.