An Area-Efficient Low-Jitter Fractional Output Divider With Replica-DTC-Free Background Calibration

This article presents an open-loop fractional output divider (FOD) that employs a replica-digital-to-time converter (DTC)-free background calibration. To support fractional division operation, the divider is modulated by a Delta-Sigma modulator (DSM). A DTC that follows the divider is incorporated to compensate for the modulation noise and generate a low-deterministic-jitter output. In this work, a background DTC gain calibration is proposed to realize a high-performance FOD. This calibration features a replica-DTC-free technique to reduce chip area and power consumption. Furthermore, a two-step division architecture is adopted to relax the tradeoffs among calibration settling time, frequency resolution, and circuit design non-idealities. Fabricated in a 90-nm CMOS process, the proposed FOD supports an output frequency range of 0.625 to 200 MHz. This FOD achieves 300 fs <tex-math notation="LaTeX">ᵣₘₛ</tex-math> integrated jitter and <tex-math notation="LaTeX">$-$</tex-math> 65 dBc spur at 192-MHz output frequency. Operated from a 1-V supply voltage, the proposed FOD consumes 1.5 mA and the core area is only 0.008 mm <tex-math notation="LaTeX">²</tex-math> .