A 66.7fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC

Modern fractional-N PLLs used as low-jitter local oscillators for wireless systems generally adopt a digital-to-time converter (DTC) to cancel-out the quantization-error (QE) induced by dithering the modulus control of the frequency divider in feedback [1], [2], [4], [5]. Unfortunately, DTC non-linearity distorts the QE sequence fed to DTC input, thus causing significant fractional spurs at the PLL output and limiting spectral purity and jitter (Fig. 1 top). The inverse-constant-slope DTC (ICS-DTC), recently introduced in [1], has improved linearity over prior-art DTC architectures; however, this comes at the price of a larger DTC jitter, caused by the current generators (CGs) adopted in that circuit. This work introduces an 8. 75–1 0.25GHz fractional-N digital PLL leveraging a resistor-based ICS-DTC circuit, which significantly improves phase-noise while retaining high-linearity. The implemented PLL prototype achieves 66. <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7fs</tex> rms jitter (including spurs), -63.BdBc fractional spur and - 108 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5dBc/Hz</tex> in-band phase noise (PN) at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10kHz</tex> offset, using a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">125MHz</tex> reference frequency.