This article presents a frequency synthesizer for generating quadrature local-oscillator (LO) waveforms covering an octave range of 6 to 12-GHz. It uses two voltage-controlled oscillators (VCO) to cover an octave range from 12 to 24 GHz. The VCOs employ inductor mode switching in addition to conventional capacitor switching to obtain a wide tuning range while maintaining a good phase noise figure of merit (FoM). Modulus-dependent delay (MDD) of the feedback divider increases jitter in fractional- <tex-math notation="LaTeX">N</tex-math> mode. The delay change can exceed 100 ps when the number of stages in the divider chain changes. A new digital technique, which can be realized with minor modifications to the conventional digital delta-sigma modulator (DDSM), is implemented to overcome this effect. The delay change is turned into a periodic error at half the reference frequency that is then filtered by the loop filter. The prototype synthesizer in 65-nm CMOS occupies 0.54 <tex-math notation="LaTeX">mm²</tex-math> and consumes 66 mW at the highest frequency from a 1-V supply, including buffers and dividers. The nominal loop bandwidth is 280 kHz. The integrated jitter is dominated by the VCOs and is 400, 300, and 500 fs in the 6 to 8-GHz, 8 to 10-GHz, and 10 to 12-GHz ranges, respectively. The worst case reference spurs are below <tex-math notation="LaTeX">-60</tex-math> dBc and the fractional spurs are below <tex-math notation="LaTeX">-31</tex-math> dBc.
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Narayanan et al. (2024) studied this question.
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