Implementation of Genetic Algorithm Accelerator on Fpga for Traveling Salesman Problem and Performing Comparative Performance Analysis

The primary objective of this study is to perform a comprehensive comparative performance analysis between traditional processor-based systems and hardware-oriented architectures for solving the Traveling Salesman Problem (TSP). On this way, a high-performance and scalable Genetic Algorithm (GA) accelerator was designed and implemented on a Xilinx Artix-7 Field-Programmable Gate Array (FPGA) using VHSIC Hardware Description Language (VHDL). The proposed architecture employs a Dual-Port Block RAM (BRAM) structure and a 4-stage parallel pipeline to overcome the computational bottlenecks and memory access latencies inherent in serial Central Processing Units (CPU) execution. The performance of the developed system was benchmarked against a Python-based CPU implementation using TSPLIB datasets. Experimental results reveal that the FPGA-based accelerator provides a big advantage, achieving a speedup ratio of up to 121.24x on used datasets. This comparative analysis demonstrates that the proposed hardware-based approach offers a superior, cost-effective, and deterministic alternative to software-based solutions for real-time optimization and Edge AI applications.