Evaluates performance of reconfigurable transistors for enhanced sensor processing, suggesting practical applications in optoelectronics.
The explosive growth of analog visual data magnifies the von Neumann bottleneck, where physically separated sensing and processing units incur prohibitive data movement. A near‐sensor architecture can mitigate this by carrying out low‐level processing (LLP) at or adjacent to the sensor, but practical hardware that unifies LLP with high‐level processing (HLP) on a scalable, singular platform based on standard fabrication processes remains hindered. Here, we report an operational design for a solution‐processed indium oxide‐based reconfigurable transistor that embeds alternative dual functionality in a single device: a visual sensor with an in‐sensor LLP/memory function and an electrical synaptic device for an HLP function. Terminal‐selective control of the ionic polarization yields two elemental behaviors: diode‐like rectification (>10 4 ) and transistor operation (apparent mobility = 37.5 cm 2 V − 1 s − 1 ), respectively. Notably, the drain pulses confine electrochemical doping–induced conductance changes to a narrow window, enabling passive in‐sensor LLP that experimentally enhances contrast in ultraviolet sensory signals. In contrast, the global gate pulses produce long‐term synaptic plasticity with a 7‐bit multi‐state and a dynamic range of ≈ 365, demonstrating that the same single‐gate platform can alternatively serve as a near‐sensor HLP unit.
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Min et al. (2026) studied this question.
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