The rapid expansion of the Internet of Things (IoT) has intensified the demand for efficient and secure cryptographic solutions. To address the stringent performance requirements of IoT environments, this study proposes two optimised hardware architectures for the ASCON-128 lightweight authenticated cipher: a high-frequency architecture (HFA) and an area-efficient architecture (AEA). Both designs were implemented on field programmable gate array (FPGA) (Xilinx ISE 14.6) and application specific integrated circuit (ASIC) (Cadence Genus 180 nm) platforms. Results demonstrate that the HFA significantly outperforms state-of-the-art designs in maximum operating frequency, while the AEA achieves a lower area footprint (slice count) compared to existing literature. The results of HFA show a promising increase in maximum operating frequency in contrast to cutting-edge designs. The AEA utilises a smaller number of slices in contrast to cutting-edge designs.
Pallavi et al. (Thu,) studied this question.