Modern computing systems are fundamentally constrained by the limitations of the classical von Neumann architecture, particularly the separation between memory and computation. As computational workloads increasingly become data-intensive, especially in artificial intelligence, scientific computing, real-time analytics, robotics, and autonomous systems, the energy and latency costs associated with data movement have emerged as dominant bottlenecks. Simultaneously, the slowing progression of Moore’s Law and Dennard scaling has exposed the limitations of relying solely on transistor miniaturization for performance improvement. This paper proposes a unified post–von Neumann computing architecture that integrates three foundational principles: memory-centric computing, dataflow-driven execution, and heterogeneous compute fabrics. The proposed architecture aims to minimize data movement, maximize parallel execution efficiency, and dynamically adapt computational resources to workload characteristics. Unlike narrow accelerators designed for specific applications, the proposed model is intended as a general-purpose computing framework capable of supporting future large-scale computational demands. The paper analyzes the architectural limitations of classical systems, examines emerging alternatives, formally defines the proposed architecture, and evaluates its theoretical advantages in terms of energy efficiency, scalability, throughput, and latency. Furthermore, the paper discusses practical implementation challenges, software ecosystem requirements, and future research directions. Keywords: Post–von Neumann Architecture, Memory-Centric Computing, Dataflow Computing, Heterogeneous Computing, In-Memory Computing, Next-Generation Computing Systems, Parallel Computing, AI Hardware.
Fahad Kareemuddin (Sun,) studied this question.