This repository HybridCPU-v2 contains the software instruction set emulator (ISE) and the accompanying architectural report for the HybridCPU v2 model. The project studies a bounded, bundle-first execution model for typed 4-Way SMT/VLIW-style packing over a live PRF/rename-backed backend substrate. Rather than relying purely on hidden-window out-of-order execution or compiler-closed static packets, HybridCPU implements an explicit runtime-owned legality model. Its central scheduler contour separates class-level admission from concrete lane materialization, mapping execution to a fixed typed W=8 lane substrate. Key Architectural MechanismsRuntime-Owned Legality: Final admissibility is evaluated dynamically under residual typed capacity, ownership domains, and live pressure state, rather than assigning absolute correctness authority to compiler-emitted packet facts. Two-Stage Admission: A typed-slot path distinctly separates class-level capacity admission (Stage A) from concrete physical lane materialization (Stage B). Bounded Replay Reuse: Replay stability and loop-buffer execution are invalidation-driven, requiring matching phase keys, structural identity, and boundary state to permit legality-template reuse. Governed Assist Plane: Auxiliary data-movement work shares the typed substrate under explicit quota and backpressure boundaries, remaining explicitly non-retire-visible.
Yuriy A.K. (Sun,) studied this question.