Efficient shared-multiplier mixed-radix FFT architecture with dynamic resource scheduling for ultra-high-speed OFDM systems

This paper presents an enhanced shared-multiplier scheduling scheme (e-SMSS) for ultra-high-speed Fast Fourier Transform (FFT) and Inverse FFT (IFFT) processors targeting next-generation optical and millimeter-wave OFDM standards. Building upon the mixed-radix multipath delay commutator (MRMDC) framework, the proposed architecture introduces dynamic twiddle-factor sharing and pipelined multiplier reuse across stages, reducing the complex multiplier count by 36% compared to prior works while supporting 128/256/512/1024-point transforms. The design employs eight parallel data paths with reconfigurable butterfly units and a multicycle scheduling controller that orchestrates multiplier access without throughput loss. The proposed design was synthesized using Xilinx Vivado on Veterx-7 FPGA, the processor achieves a 40 GS/s throughput at 500 MHz. Synthesizable Verilog models for the core butterfly, shared multiplier array, and scheduling controller were provided and validated.