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June 16, 2008IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems348 citations

NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints

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TCTung-Chieh ChenZJZhewei JiangTHTien-Chang Hsu

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Abstract

In addition to wirelength, modern placers need to consider various constraints such as preplaced blocks and density. We propose a high-quality analytical placement algorithm considering wirelength, preplaced blocks, and density based on the log-sum-exp wirelength model proposed by Naylor and the multilevel framework. To handle preplaced blocks, we use a two-stage smoothing technique, i.e., Gaussian smoothing followed by level smoothing, to facilitate block spreading during global placement (GP). The density is controlled by white-space reallocation using partitioning and cut-line shifting during GP and cell sliding during detailed placement. We further use the conjugate gradient method with dynamic step-size control to speed up the GP and macro shifting to find better macro positions. Experimental results show that our placer obtains very high-quality results.

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Chen et al. (2008) studied this question.

synapsesocial.com/papers/6a07459902b4a6d6a3d3ee61https://doi.org/10.1109/tcad.2008.923063
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