LightPlace: A Lightweight and Connectivity-Aware Macro Placement Framework for Mixed-Size 3-D ICs

As integrated circuit design continues to scale, three-dimensional integrated circuit (3D-IC) technology has emerged as a promising solution to extend Moore’s Law. Among various physical design stages, placement plays a pivotal role, directly influencing key power, performance, and area (PPA) metrics. In research that does not consider specific 3DIC process technologies, the state-of-the-art ePlace-3D introduces 3D electrostatic field density modeling, enabling nonlinear placement algorithms to truly address 3D placement problems. However, its complex flow results in low runtime efficiency. In this work, we propose LightPlace, a lightweight and effective 3D placement framework. This framework incorporates Virtual Macro Insertion approach and Macro Connection Reconstruction method, which streamline the macro placement phase and allocate space for subsequent standard cell placement. These innovations enhance runtime efficiency and optimize wirelength. Experimental results on the large-scale Modern Mixed-Size (MMS) benchmarks demonstrate that, LightPlace reduces total wirelength by an average of 10% and achieves up to 4× faster runtime compared to the runtime reported for ePlace-3D.