As a critical step in the chip design flow, logic synthesis generates target circuits by iteratively applying various optimization algorithms. In practical applications, engineers must adjust the combination of optimization algorithms based on expert knowledge to meet diverse design requirements. However, existing approaches lack a multi-objective optimization perspective and exhibit poor solving efficiency. In light of this, we propose DSETune, the first synthesis flow search approach capable of thoroughly exploring the design space. First, a discrete particle swarm optimization algorithm incorporating genetic operators significantly improves search efficiency of design space. Second, a domain knowledge-driven initialization strategy of particles accelerates convergence and enhances solution quality. Finally, an update mechanism integrating a customized elite strategy enables more comprehensive solution space exploration, yielding superior Pareto-optimal solutions. Experimental results on the EPFL benchmark suite and four technology libraries demonstrate that DSETune outperforms existing methods: it reduces the area-delay product by 10.99%, improves the hypervolume metric by 109.80%, and achieves a 22.99% speedup, all on average.
Zhang et al. (Thu,) studied this question.