Simultaneous effects of temperature and magnetic flux on a network of Huber–Braun neurons: Modeling and hardware implementation results

This paper investigates the simultaneous effects of temperature and electromagnetic flux on the dynamics of a network of Huber–Braun (HB) neuron models. The model incorporates memristive feedback to emulate electromagnetic flux and temperature-dependent scaling to modulate ion-channel kinetics. Results show that increasing temperature shifts activity from low-frequency bursting to high-frequency tonic spiking, whereas stronger magnetic flux coupling suppresses spiking, indicating a quenching effect. Sensitivity analysis reveals that electromagnetic flux improves robustness by reducing sensitivity to input-current fluctuations. Noise analysis indicates that memristive feedback yields a more gradual response to stochastic perturbations than the non-memristive case. At the network level, simulations on a 150 × 150 lattice reveal spatiotemporal patterns, including spiral waves, whose stability and morphology depend on the coupling coefficient, stimulus amplitude, and frequency. Strong coupling promotes synchronized wave propagation. Two Field-Programmable Gate Array (FPGA) realizations are presented: an accurate HB design and a hardware-optimized approximated HB (AHB) model. On Virtex-6, AHB reduces slice registers by 10.76%, Look-Up Table Flip-Flop (LUT-FF) pairs by 15.89%, and slice LUTs by 1.22%, while increasing the maximum frequency from 145.21 MHz to 235.24 MHz (61.98%). Overall, AHB achieves high-speed, resource-efficient neuromorphic hardware without sacrificing dynamical accuracy. • Effects of temperature and EM flux on a memristive Huber–Braun neuron are studied. • Noise robustness and firing rates analyzed vs. thermal and EM coupling strengths. • First spatiotemporal study of the HB model on a 150 × 150 neuronal network. • First high-speed FPGA implementation of the HB model for neuromorphic systems. • Efficient AHB model achieves higher speed and lower hardware costs on FPGA.