The electroless gold plating process developed in this laboratory has been successfully applied to the fabrication of beam leads on silicon integrated circuits. This unique plating process selectively plates gold onto discrete patterned regions of a substrate at 6 µm/hr with ≤10% thickness nonuniformity for thicknesses of 10–12 µm. Beam lead patterns were formed either by vacuum evaporation of titanium followed by palladium through a metal shadow mask or by photolithography and etching. The compatibility of this processing with a number of other materials present on Si devices has been established. Beam lead structures have been characterized with respect to mechanical properties and found to meet or exceed system requirements. This process is shown to be capable of high yields and is an attractive alternative to conventional methods of fabricating beam leads.
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Sard et al. (1974) studied this question.