5–10 Gb/s 70 mW Burst Mode AC Coupled Receiver in 90-nm CMOS

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A low power burst mode receiver architecture is presented which can be used for AC coupled links where low frequency signal components are attenuated by the channel. The nonlinear path comprises a hysteresis latch that recovers the missing low frequency content and a linear path that boosts the high frequency component by taking advantage of the high pass channel response. By optimally combining them, the front-end recovers NRZ signals up to 13 Gb/s burning only 26 mW in 90 nm CMOS. A low power- and area-efficient clock recovery scheme uses the linear path to injection lock an oscillator. A simple theory and simulation technique for ILO-based receivers is discussed. The clock recovery technique is verified with experimental results at 5–10 Gb/s in 90 nm CMOS consuming 70 mW and acquiring lock within 1.5 ns. </para>