HLS-Based FPGA Implementation of Convolutional Deep Belief Network for Signal Modulation Recognition

Deep learning method is widely applied in modern artificial intelligence technology for Signal Modulation Recognition (SMR). Compared to CPUs and GPUs, FPGAs are highly energy-efficient and have low-latency streaming capabilities, which are more suitable for energy-sensitive or real-time machine learning projects. High-level synthesis (HLS) can automatically convert the logical structure described by a high-level language into a description by a low-level abstraction language. In this paper, we propose a system to optimize Deep Confidence Network (CDBN) by loops pipelining and unroll, memory buffering and partitioning, and implement an energy-efficient HLS-based FPGA Convolutional CDBN accelerator for SMR based on Virtex-7 platform. The accelerator system run at 150MHz and has 28% higher throughput and 80.5% less power consumption than a GPU implementation.