This article consists of a collection of slides from the author's conference presentation on the special features, system design, processing capabilities, and targeted markets for Movidius's 1TOPS/W, a software programmable media processor.

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Cite This Study

David Moloney (Mon,) studied this question.

synapsesocial.com/papers/6a12708a19b8e1960734b803 https://doi.org/https://doi.org/10.1109/hotchips.2011.7477507

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5A 4.2GHz 0.3mm2 256kb Dual-V/sub cc/ SRAM Building Block in 65nm CMOS2006 · 31 citations

Also Consider

Synapse has enriched 5 closely related papers on similar clinical questions. Consider them for comparative context:

1A 275mW heterogeneous multimedia processor for IC-stacking on Si-interposer2011 · 10 citations
2A fast algorithm for the conversion of DCT coefficients to H.264 transform coefficients2005 · 8 citations
3An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS2007 · 634 citations
4Networks on chips: a new SoC paradigm2002 · 3,749 citations
5A 4.2GHz 0.3mm2 256kb Dual-V/sub cc/ SRAM Building Block in 65nm CMOS2006 · 31 citations